Event Details

Architectural Enhancements for Message Passing Interconnects (A.K.A. Network Processors)

Presenter: Dr. Nikitas Dimopoulos - Professor and Chair, Electrical and Computer Engineering, University of Victoria
Supervisor:

Date: Thu, September 19, 2002
Time: 14:00:00 - 15:00:00
Place: EOW 430

ABSTRACT

Abstract:

With the increasing uniprocessor and SMP computation power available today, inter-processor communication has become an important factor that limits the performance of clusters of workstations. Many factors including communication hardware overhead, communication software overhead, and the user environment overhead affect the performance of the communication subsystems in such systems.

A significant portion of the software communication overhead is due to the number of message copying. Ideally, it is desirable to have a true zero-copy protocol where the message is moved directly from the send buffer in its user space to the receive buffer in the destination without any intermediate buffering. However, due to the fact that message-passing applications at the send side do not know the final receive buffer addresses, early-arriving messages have to be buffered at a temporary area, thus giving rise to delays because of extra copying.

In this presentation, we show that there is a message reception communication locality in message-passing applications. We have utilized this communication locality and devised different message predictors at the receiver sides of communications. In essence, these message predictors can be efficiently used to drain the network and cache the incoming messages even if the corresponding receive calls have not been posted yet. We also introduce specific extensions to an ISA and processor architecture to accommodate late binding without requiring copying of the message, and thus achieve zero-copy communications.

For Further Information Contact Dr. Jens Bornemann (721-8666)