Event Details
PUF Evaluation Metrics on Xilinx 7 Series FPGAs : Comparative Analysis of Arbiter, XOR Arbiter, and Double Arbiter PUFs for Uniqueness, Randomness, and Stability
Presenter: Janviben Lunagariya
Supervisor:
Date: Mon, January 8, 2024
Time: 10:00:00 - 00:00:00
Place: Zoom- see below
ABSTRACT
Zoom Details:
https://uvic.zoom.us/j/87541251226?pwd=UDB3YytQMkhTSUlVMFVFbmdsaFUxUT09
Meeting ID: 875 4125 1226
Password: 319126
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Meeting ID: 875 4125 1226
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ABSTRACT: Physical Unclonable Functions (PUFs) are specialized circuit components leveraging microchip fabrication variations to create unique fingerprint-like responses to specific inputs. These device-specific variations make PUFs ideal for cryptographic key generation due to their difficulty in replication, even by the original manufacturer. Arbiter-based PUFs, specifically on Xilinx Virtex-5 FPGAs, initially exhibited low uniqueness. To address this, variants like XOR Arbiter PUF and Double Arbiter PUF were introduced, offering highly unique responses on FPGAs at a comparable cost. This study evaluates these PUFs on Xilinx 7-series FPGAs, introducing the 3-1 Double Arbiter PUF as a new mode. Compared to the conventional Arbiter PUF and 3-XOR Arbiter PUF, it demonstrates better response uniqueness and randomness (50%), highlighting the potential for improved PUF evaluation metrics with this new mode of operation.