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Presenter: Narges Attarmoghaddam
Supervisor:

Date: Wed, August 10, 2022
Time: 11:00:00 - 12:00:00
Place: ZOOM - Please see below.

ABSTRACT

https://uvic.zoom.us/j/88444732075?pwd=cC9BdjJxZ0gxczhxNWxWeXVodlhSQT09

Meeting ID: 884 4473 2075
Password: 284349

Note: Please log in to Zoom via SSO and your UVic Netlink ID.

ABSTRACT

Image classification is an active research area in computer vision with many applications. Image classification is a computationally complex task, but only limited resources are allowed for embedded applications. Moreover, additional constraints such as reliable classification accuracy, high-throughput performance, power-efficient, and real-time computing must be fulfilled. Due to the potential for parallelism, low power consumption, scalable resource utilization, and reconfigurability, Field Programmable Gate Array (FPGA) devices are well-suited to overcome these challenges in image classification system implementation.
We implemented a multi-class feature-based image classification system using binary feature sets. A binary feature of an image pixel is represented using one bit, while a non-binary feature is represented using more bits. Therefore, implementing an image classification system based on a binary feature set needs fewer hardware resources for storage and computation.
Using a binary feature set generally leads to an area-efficient and faster architecture; however, accuracy is lost because binary features contain less information than non-binary features. We proposed a dual-feature system that combines HOG and LBP features to improve classification accuracy performance. The SVM classification algorithm is utilized as the classifier in the proposed system. To obtain binary features, two steps of binarization are applied to the HOG descriptor. First, HOG features are extracted from binary images to simplify the feature extraction process. Second, the block histogram normalization of both HOG and LBP descriptors is replaced with binarization to reduce hardware resource utilization in the descriptors and the SVM classifier.
Binary-based computation in the proposed system reduces resource utilization, thus allowing an area-efficient architecture even with two feature descriptors implemented. Compared to similar existing works, our system speeds up the classification process while utilizing fewer hardware resources, with comparable accuracy.